Here’s a for Synopsys Design Compiler (DC) — focusing on the key features you’ll actually use to synthesize RTL to a gate-level netlist.
Check:
# .synopsys_dc.setup set search_path [list . ./rtl ./lib] set target_library "saed90nm_typ.db" set link_library [list "*" $target_library] set symbol_library "saed90nm.sdb" set synthetic_library "dw_foundation.sldb" dc_shell -topo # for topographical mode (more accurate) dc_shell # normal mode 2. Read RTL Design # Read all Verilog/VHDL files read_verilog top_module.v sub_module1.v sub_module2.v Or use analyze & elaborate (for VHDL/Verilog with parameters) analyze -format verilog -lib WORK file1.v file2.v elaborate top_module synopsys design compiler tutorial
Here’s a for Synopsys Design Compiler (DC) — focusing on the key features you’ll actually use to synthesize RTL to a gate-level netlist.
Check:
# .synopsys_dc.setup set search_path [list . ./rtl ./lib] set target_library "saed90nm_typ.db" set link_library [list "*" $target_library] set symbol_library "saed90nm.sdb" set synthetic_library "dw_foundation.sldb" dc_shell -topo # for topographical mode (more accurate) dc_shell # normal mode 2. Read RTL Design # Read all Verilog/VHDL files read_verilog top_module.v sub_module1.v sub_module2.v Or use analyze & elaborate (for VHDL/Verilog with parameters) analyze -format verilog -lib WORK file1.v file2.v elaborate top_module